1. Field of the Invention
The present invention relates to an electronic device substrate, an electronic device and methods for fabricating the same, and in more particularly, to an electronic device substrate, an electronic device substrate, and methods for fabricating the same, that enable a core substrate-less package having an internal electrical wiring, in which a load of a process of removing a core substrate is reduced, by using a physical peeling off as well as a chemical dissolution, an electrochemical dissolution, or a mechanical polishing process.
2. Description of the Related Art
In accordance with technical development of recent years, a miniaturization of a package for an electronic device has been requested, so that an electronic device of so-called “core substrate-less package” is put to practical use.
As an example of typical core substrate-less packages, a conventional electronic device is described in Japanese Patent Laid-Open No. 2004-253674 (JP-A-2004-253674, FIG. 3). This electronic device is fabricated as follows. Electronic parts are mounted on a substrate comprising a core substrate and a metal electrode connected on the core substrate, and a predetermined electrode is electrically connected to the electronic parts by a thin metallic wire and sealed by a resin. Thereafter, the core substrate is physically peeled off, so that the metal electrode is exposed to a lower surface (back surface) of the package.
Since this electronic device is covered with the sealing resin and has a leadless structure in which the metal electrode is exposed at the back surface, a substrate part is only the metal electrode, so that this electronic device is very thin.
In addition, as another example of the core substrate-less package, another conventional electronic device is proposed by Japanese Patent Laid-Open No. 2004-111536 (JP-A-2004-111536, FIG. 1).
In this electronic device, a first wiring layer is disposed on a first interlayer insulating layer, a second interlayer insulating layer is disposed thereon, the second interlayer insulating layer is provided with an opening at a predetermined position, a via-conductor is disposed at the predetermined position, and interlayer insulating layers each having a wiring layer and a via-conductor are sequentially disposed thereon for a desired number of times, and a metal supporting frame is provided on the layers, to provide a substrate configuration.
In the Japanese Patent Laid-Open No. 2004-111536 (paragraph [0038]), the electronic device is construed by a general flip-chip fabrication method in which a semiconductor is further connected to this substrate via a metal bump.
However, according to the configuration disclosed in Japanese Patent Laid-Open No. 2004-253674, since no supporting member is provided in a circumference of the metal electrode, there is a disadvantage in that the multilayer wiring is difficult.
In addition, according to the configuration disclosed in Japanese Patent Laid-Open No. 2004-111536, the multilayer wiring is possible by virtue of the interlayer dielectric layer. However, a very thin substrate such as the electronic device disclosed in Japanese Patent Laid-Open No. 2004-253674 cannot be realized.
As thus described, there is the first problem in that a very thin substrate generally used in the typical core substrate-less package is not compatible with the multilayer wiring configuration. This is caused by forming the via-conductor for constituting the multilayer wiring configuration. The reason will be described in more detail as follows.
As described above, the multilayer substrate can be fabricated by virtue of the existence of the interlayer insulating layer in the configuration disclosed by Japanese Patent Laid-Open No. 2004-253674. However, since this multilayer substrate has a configuration in that copper layers are laminated on a top surface and a bottom surface of the interlayer insulating layer for each of single layer plates and the wiring pattern is disposed thereon, the via-conductor for connecting between the wiring patterns on the top and bottom surfaces is required.
FIGS. 18A to 18C are cross sectional views for briefly explaining a process for via processing and conductive plating.
At first, copper layers 62 are laminated at a top surface and a bottom surface of an interlayer insulating layer 61 in a substrate as shown in FIG. 18A, and a via 63 is formed as shown in FIG. 18B. Next, as shown in FIG. 18C, a conductive plating 64 is provided for connecting the copper layers 62 (wiring patterns) at the top and bottom surfaces around the via 63. This means that a total thickness of the upper and lower wiring patterns is required in addition to a thickness of the interlayer insulating layer 61 for a total thickness of each of the single layer plates. Furthermore, when a conductor (generally composed of copper) is provided by plating at side surfaces of the via 63 in course of the via-conductor preparation, circulation of a plating liquid is not good due to a minute bore, and a plating growth is difficult since the plating is provided on an insulating material. Therefore, a plating thickness is required to be about 10 μm on the wiring pattern for obtaining a bonding reliability. Accordingly, a total thickness of the wiring pattern is generally about 25 to 30 μm, as a result of addition of the plating thickness to the thickness of the wiring pattern originally provided. For fabricating the multilayer substrate, the thickness of the wiring pattern is required for the number of wiring pattern layers.
The second problem is that a size of a wiring part is large. This is also caused by the via-conductor. The reason is that a wiring pattern forming process is not the same process as a via boring process, dimensions of formed articles should have allowance for absorbing a gap between positions of each of the formed articles in these two processes.
FIG. 18D is a schematic plan view of a periphery of a via.
When a conductive part (via-land 65) is positioned to surround around the via 63 and a pattern (wiring 66) conducted from a part of the via-land 65 is laid out, the via-land 65 is generally formed to have an allowance of about 50 μm greater than a via diameter at one side, and of about 100 μm greater than the via diameter, with considering a positioning precision in the via formation and a positioning precision in the pattern formation, for securely connecting the wiring pattern to be connected to the via-conductor.
In addition, there is so-called flip-chip method for connecting the substrate to the electronic part via the bump, as a method for reducing a size and a thickness of the electronic device. According to this method, bonding electrodes for the substrate can be formed inside the electronic part, so that the electronic device can be miniaturized compared with a case where the electronic part and the substrate are connected with each other via a thin metallic wire. Further, when the above described bonding is conducted by using the metallic wire, a height for installing the thin metallic wire is necessary. In the flip-chip method, this height for installing the thin metallic wire is only a height for installing the bump, so that the miniaturization can be realized. On the other hand, in the flip-chip method, the electrode in the electronic part is small by reason of the minute processing and an interval between the electrodes is dense. Therefore, it is necessary to actually form an internal wiring on the substrate and to determine a position of an external electrode such that the external electrode can be mounted on a mother board for mounting the electronic device, so as to provide the electronic device. Accordingly, forming a thin and small substrate similar to a typical substrate-less package to have multilayers means that the flip-chip method can be adopted in the general core substrate-less package, and it is very important to promote the small sizing and miniaturization of the electronic device.